The present invention relates to a nonvolatile semiconductor storage device. More particularly, the present invention relates to a NAND cell type of EEPROM (Electrically Erasable Programmable Read Only Memory) which has an STI (Shallow Trench Isolation) structure and uses memory cells which permit two or more valued data to be electrically rewritten into through the use of techniques of writing into the floating channel.
Conventionally, as a nonvolatile semiconductor storage device which is electrically rewritable and allows a high packing density, a NAND cell type of EEPROM is known in which a plurality of memory cells are connected in series. In this semiconductor storage device, each of the memory cells has a stacked gate structure in which a floating gate and a control gate are stacked with an insulating film interposed therebetween. In addition, the memory cells are connected in series in such a way that adjacent cells share a source/drain diffused region. The memory cells that are connected in series forms a unit. The memory cells as a unit are connected to a bit line (data line), forming a NAND type cell (hereinafter referred to as a NAND cell). The NAND cells are arranged in a matrix to form a memory cell array.
That is, each of NAND cells arranged in each column in the memory cell array has a drain diffused region at its one end connected to a bit line through a select gate and a source diffused region at its other end connected to a common source line (reference potential supply line) through a select gate. The control gates of memory cells arranged in a row are connected in common to a control gate line (word line) and the control electrodes of select gates arranged in the row direction are connected in common to and a select gate line.
If, in the NAND cell type of EEPROM, lower voltage operation were realized, a column decoder connected to the bit lines could be formed from Vcc-operated transistors. This would help reduce the area of peripheral circuitry and the chip size.
From this point of view, in recent years, a floating channel writing method has been proposed and put to practical use. The floating channel writing method is described as follows.
FIG. 1 shows an equivalent circuit of the memory cell section of a NAND cell type of EEPROM. In this figure, BL (BL1, BL2, BL3, . . . ) denotes a bit line, SG (SG1, SG2) denotes a select gate, CG (CG1 to CGn) denotes a word line, and SL denotes a source line.
In normal data write operations, the cells are written into in the order of arrangement beginning with the cell that is the farthest from the corresponding bit line BL. In random writing, on the other hand, the cells between the bit line BL and the source line SL are written into in a random order. First, 0 volts are applied to the select gates on the source line SL side to turn their associated transistors off. In this state, 0 volts are applied to a bit line BL associated with a NAND cell containing a memory cell into which a 0 is to be written. To a bit line associated with a NAND cell containing a memory cell into which a 1 is to be written is applied a voltage which is larger than or equal to the select gate voltage on the drain diffused region side. In this manner, a selection between writing and nonwriting is made for each bit line. Alternatively, by applying to the bit line a potential which, even if it is lower than the select gate voltage on the drain diffused region side, permits the select gate SG to turn off, a selection between writing and nonwriting is made for each bit line.
That is, in this state, a potential that permits memory cells to turn on is applied to all the word lines CG in a selected block (when a write voltage Vpp or a nonselected word-line voltage Vpass is applied, memory cells are brought to the on state at a certain potential when the voltage pulse is increasing to a maximum). Then, 0 volts are transferred to the channel of a NAND cell connected to a bit line for writing a 0. On the other hand, to the channel of a NAND cell connected to a bit line for writing a 1 a certain initial potential (the potential on that bit line minus the threshold of the select gate) is transferred from that bit line through the select gate SG on the bit line side. Thus, the NAND cell connected to the bit line for writing a 1 become floating. At this point, 0 volts or a certain positive potential is applied to the source line SL to turn off the select gate on the source diffused region side.
Next, the write voltage Vpp is applied to a selected word line associated with the memory cell into which a 0 is to be written. As a consequence, a 0 will be written into the selected memory cell that is connected to the selected bit line supplied with 0 volts. At this point, it is required that the channel potential of nonselected memory cells which are associated with the selected word line but are not to be written with a 0 (memory cells in which their associated select gates SG on the bit line side are turned off and hence their channels are in the floating state) be sufficiently large so that a 0 will not be written into (so that variations in threshold will fall within an allowable range). In the case of these memory cells, as the difference between the write voltage Vpp and the channel potential Vch becomes smaller, variations in threshold become smaller. For this reason, a certain voltage Vpass is applied to nonselected word lines which are not associated with a memory cell into which a 0 is to be written. By so doing, the channel potential of the memory cells is increased from an initial potential to a certain potential by capacitive coupling of their floating channels with the nonselected and selected word lines. In this case, the greater the voltage Vpass, the smaller the variations in threshold become.
Of memory cells connected with the selected bit line supplied with 0 volts, memory cells into which a 0 is not to be written are also supplied with the voltage Vpass. In this case, the greater the voltage Vpass, the easier the variations in threshold become to occur.
Thus, the minimum and maximum values of the voltage Vpass are determined taking these conditions into consideration. In order to reduce the variations in the threshold of memory cells into which a 0 is to be written and errors associated with writing, a step-up method is normally employed in which the voltages Vpass and Vpp are each optimized for their initial voltage, step voltage, final voltage, and pulse width.
Data erase includes batch erase by which all the memory cells of a NAND cell are simultaneously erased and block erase in byte units. In the case of batch erase, all the control gates (or all the control gates in a selected block) are set to 0 volts and all the selected gates SG are supplied with the voltage Vpp or placed in the floating state. The bit lines and the source line SL are made floating and P-well regions are impressed with a high voltage of, for example, 20 volts. Thereby, in all the memory cells (or all the memory cells in a selected block), electrons are forced from the floating gate into the P-well region, shifting the threshold in the negative direction. In the case of block erase, it is required that the control gates in a nonselected block be impressed with a high voltage of, for example, 20 volts or maintained floating.
For data reading, a read voltage (for example, 4.5 volts) is applied to the select gates SG1 and SG2 and the word lines CG associated with nonselected memory cells other than a selected memory cell, thereby turning the nonselected memory cells on. On the other hand, 0 volts are applied to the word line associated with the selected memory cell. By sensing a current flowing through the bit line, discrimination between a 0 and a 1 can be made.
Such a NAND cell type EEPROM writing method (floating channel writing method) conventionally used suffers from the problems described below.
FIG. 2 shows an equivalent circuit of a NAND cell type of EEPROM to describe the memory cell operation at the time of writing into the floating channel. Here, a write-selected memory cell A and a nonselected memory cell B are illustrated by way of example. With the write selected memory cell A into which a 1 is to be written, its channel is maintained floating and its associated word line CG is impressed with the voltage Vpp. With the nonselected memory cell B, its associated bit line BL is impressed with 0 volts and its associated word line CG is impressed with the voltage Vpass. V.sub.BL (V.sub.BL1, V.sub.BL2, V.sub.BL3 . . . ) denotes a voltage applied to a bit line BL, V.sub.SG (V.sub.SG1, V.sub.SG2) denotes a voltage applied to a select gate SG, V.sub.CG (V.sub.CG1 to V.sub.CGn) denotes a voltage applied to a word line CG, and V.sub.SL denotes a voltage applied to the source line SL. Although, in this example, the second memory cell counting from the bit line side is made the selected memory cell A, an arbitrary memory cell is selected during normal writing operation.
FIG. 3 shows voltage waveforms applied to the respective electrodes to describe the operation of the circuit shown in FIG. 2. First, the bit line BL1 is impressed with either 0 volts or supply voltage Vcc (for example, 3.3 volts), depending on data to be written into, the source line SL and the select gate SG1 on the bit line side are impressed with the supply voltage (3.3 volts), and the select gate SG2 on the source diffused region side is impressed with 0 volts. In this state, the channel of the NAND cell associated with the bit line BL1 into which a 0 is not written becomes floating. After that, the selected word line CG2 is impressed with voltage Vpp and the nonselected word lines CG1, CG3 to CGn are impressed with voltage Vpass, booting the floating channel to a certain potential Vch. The channel potential Vch and the potentials of the respective electrodes are related by ##EQU1##
where V.sub.SG th(Vchinit) is the threshold of the select gate SG1 on the drain diffused region side when the channel potential is Vchinit, Cr1 is the boot ratio of the channel (the ratio between the capacitance associated with the memory cell impressed with voltage Vpp and the capacitance associated with the depletion layer extending below the channel due to voltage Vpp), and Vpassth(Vch) is a potential required to turn on the memory cell impressed with voltage Vpass when the channel potential is Vch.
In this case, however, a decrease in the initial voltage, Vchinit, transferred from the bit line to the channel region and a decrease in channel boot efficiency (Cr1, Cr2) due to an increase in the capacitance associated with the depletion layer below the channel and the capacitance between the 0-V terminal and the channel are liable to occur. This is due to various conditions for forming memory cells and select gates, such as impurity profiles of the select gates, the memory cells and a semiconductor substrate in which the select gates and the memory cells are formed (the impurity concentration of boron when these are formed in a P well region), the concentration of impurities introduced into the select gates and the memory cells by means of ion implantation, the impurity profiles of drain/source diffused regions of the select gates and memory cells, etc. As a result, a sufficient channel potential cannot be obtained and the threshold of a memory cell into which a 1 is written varies, which may result in a write error.
FIG. 4 shows a plot of the thresholds of the cells A and B against the voltage Vpass when such a write error occur. As can been seen from this figure, the threshold of the cell A (the memory cell into which a 1 is to be written) shifts in the positive direction (Vpass stress) when the magnitude of voltage Vpass decreases. On the other hand, the threshold of the cell B varies (Vpp stress) when the magnitude of voltage Vpass increases greatly.
The variation in threshold tends to become noticeable when there are great variations in writing characteristics, which are due to variations in the gate width, gate length, wing width, tunnel oxide thickness, interlayer polysilicon insulating film thickness of memory cells, etc. In particular, the threshold variation becomes easier to occur as the number of bits in a selected block becomes larger at the time of writing. Moreover, when leak current between the floating channel and the well region, between the source/drain region and the well region, or between adjacent bit lines is great, the threshold variation becomes still greater. Furthermore, variations in the characteristics of each select gate transistor adapted to transfer the potential on the bit line to the channel also greatly affect the threshold variations.
As described above, it is known that the memory cell and select gate transistor characteristics affect the writing characteristics as shown in FIG. 4. Improved storage devices are taught in a paper entitled "A Novel BOOSTER Plate Technology in High Density NAND Flash Memories for Voltage Scaling-Down and Zero Program Disturbance" by J. D. Choi et al, IEEE Symposium on VLSI Technology Digest of Technical Papers, 1996, pp. 238-. Also, a paper entitled "Process Integration for the High Speed NAND Flash Memory Cell" by D. J. Kim et al appears on pages 236- of the same journal.
The problems with the methods described in these papers are that processing steps become complicated, the number of processing steps increases, the chip size increases, and so on. In addition, the presence of variations in threshold greatly affect the data holding characteristics of memory cells when they are read from or in the idle state, lowering reliability.
That is, a conventional measure taken against erroneous writing is to form a booster polysilicon layer on each control gate as described in the first mentioned paper and to apply a high positive voltage of the order of 9 to 17 volts to that layer, thereby booting the channel potential of write-nonselected memory cells and improving the coupling characteristic of cells. In this manner, an improvement in write speed and compatibility with multi-valued memories can be achieved.
According to the above-described method, the degradation of the erroneous writing characteristic can be prevented, but an increase in the chip area occupied by a charge-pump circuit and row/column decoders is inevitable. An increase in the chip size will result in an increase in cost per bit.